1. Field of the Invention
The present invention relates to the field of data coding and electronic circuits. More particularly, the present invention relates to a system and a method that provides byte synchronization for detecting data using partial-response signaling with maximum-likelihood (PRML) sequence detection techniques.
2. Description of the Related Art
When transmitting data, header information is attached in front of the data to set up the receiver. Byte synchronization must be included in the header for identifying the position of the first data bit of the data bits. Such byte synchronization is sometimes called a "timing mark." In a partial-response with maximum-likelihood sequence detection (PRML) maximum recording channel, byte synchronization is used to mark the first bit of a symbol. In conventional byte synchronization techniques, special bit sequences, or patterns, that indicate beginnings of data blocks are detected by a Viterbi detector and a synchronization symbol detector. For example, in a partial-response class-IV (PR-IV or PR4) system running in 9/8 code, a 9-bit pattern, such as "111101111", is repeated three times for byte synchronization detection after the occurrence of an all "1s" bit pattern that is used for bit synchronizing a voltage-controlled oscillator (VCO). By repeating the special data sequence three times, the total length of the conventional synchronization code for the PR4 system is 27 bits.
Conventional byte synchronization also uses a 2-of-3 pattern matching voting scheme for handling situations when one of the three repeated synchronization patterns has detection errors. A synchronization detection error can be caused by a bad Viterbi input sample, for example. The occurrence of more than 2 bad input samples during synchronization detection may cause a synchronization failure (failure to realize synchronization) or a mis-synchronization condition (synchronize to a false bit position).
In a PR4 system, adjacent samples are interleaved and are independent from each other. A Viterbi detector for such a system uses two samples from the same interleaved sample group for symbol detection. In a noiseless PR4 system, all Viterbi detector input samples S.sub.i are defined to be the symbols 1, 0 and -1. The sample sequences 1, 0*, 1 and -1, 0*, -1 are not allowed in a 2-way interleaved sample group. The symbol 0*, as used herein, means: 1) the occurrence of no 0 symbol, or 2) the occurrence of equal to or more than one 0 symbol. For example, "1, -1", "-1, 0, 1" and "-1, 0, 0, 1" are allowed sequences, while "1, 1", "-1, 0, -1" and "1, 0, 0, 1" are not allowed. Due to this restriction, symbol detection error situations can be grouped by cases of symmetrical symbol sequences so that only the 4 possible cases of symbol sequences, shown in FIG. 1, need be considered.
A Viterbi input sample S.sub.i is given by EQU S.sub.i =X.sub.i +N.sub.i (1)
where X.sub.i is the originally recorded symbol value and N.sub.i represents noise, both measured in analog-to-digital converter (ADC) LSB levels. Noise N.sub.i is defined herein to be Gaussian. Viterbi detector symbol detection decisions are based on combining two samples S.sub.i-2k and S.sub.i, where k is an error separation number. If the two samples S.sub.i-2k and S.sub.i include noise N.sub.i-2k and N.sub.i, respectively, that have magnitudes causing symbol detection decision errors, the two samples are considered to be a bad sample combination. Otherwise, the samples are considered to be a good sample combination. One bad sample combination causes two code bit errors. Exemplary good and bad sample combinations are shown in FIGS. 2-5 for each of the four cases shown in FIG. 1.
The Viterbi detector difference metric DJ.sub.i-2k is based on previous samples. For the exemplary analog-to-digital converter (ADC) output having a sample sequence 16, 0, -16 corresponding to the symbol sequence 1, 0, -1, if symbol sample S.sub.i is within .+-.8 LSBs from DJ.sub.i-2k, then DJ.sub.i is equal to DJ.sub.i-2k. So, if a 0 symbol is detected k+1 times consecutively, where k&gt;1 (FIG. 5B), the detection decision is based on S.sub.i and the previous potential maximum or potential minimum sample S.sub.i-2k. In other words, the bad sample combination includes two noise values N.sub.i-2k and N.sub.i that have a difference that is greater than or equal to 16 LSBs. For example, in FIG. 2B, the bad sample combination includes noise samples N.sub.i-2k =10 and N.sub.i =-8. The difference between the two noise samples is greater than 16, and is large enough to cause detection errors.
Based on this, the probability (P.sub.err) of a bad sample combination for a Viterbi detector can be expressed by: ##EQU1## where the term P(N.sub.i =j) is the probability that the noise N.sub.i equals j.times.LSB, and the term P(N.sub.i-2k .gtoreq.j+16) is the probability that the noise N.sub.i-2k is greater than or equal to (j+16).times.LSB. While the summation range is different for each of the four cases, the probability of a bad sample combination for each of the four cases is expected to be almost the same because P(N.sub.i =j) is so small that it can be neglected when the absolute value of j becomes large. For example, P(N.sub.i =16)=5.1.times.10.sup.-8 at a signal-to-noise ratio (SNR) of 16 dB. The Viterbi detector error probability (P.sub.err) can be estimated for any case using Equation (2) and is plotted in FIG. 6.
FIG. 7 shows a schematic block diagram for a conventional byte synchronization circuit 70. Circuit 70 uses a 7-bit shift-register 71, a pattern matching gate 72, a latch L1 and an 18-bit shift-register 73. FIG. 8 shows a timing diagram for circuit 70. To implement correct byte synchronization, a write circuit (FIG. 9) includes a magnet trimming circuit. The magnet trimming circuit changes the write data path delay depending upon the precoder's initial values when the byte synchronization pattern is applied to the circuit. FIG. 9 shows a schematic block diagram of a conventional write circuit 90 having a magnet trimming circuit 91 and a precoder circuit 92 that operate in conjunction with circuit 70. FIG. 10 is a diagram of possible magnet patterns for magnet trimming circuit 90 for the 4 cases, which gives the same output codes in FIG. 8 (111 . . . 1111011111111011111111011111). The write circuit adjusts the write path delay so that either pattern (1) or (2), shown in FIG. 10, is written because circuit 70 can detect byte synchronization only for these two patterns, not for patterns (3) and (4) shown in FIG. 10. A mod-2 sync phase control signal is generated by dividing the data clock in circuit 70 by two and is used for achieving correct byte synchronization.
For the conventional system shown in FIGS. 7-10, 7 internal bits are used for pattern matching for each 9-bit pattern because the error separation number k in Equation (2) is likely to be 1 when no 0 bit occurs in the code bit pattern. Consequently, a single bad bit sample does not destroy two adjacent 9-bit synchronization sequences simultaneously. Nevertheless, the one bad bit sample destroys one adjacent synchronization byte sequence. For example, an error at the eighth bit of a 9-bit code pattern is likely to occur with an error at the first bit of the subsequent code pattern because there is no 0 bit at either the beginning or the end of the synchronization code. Since the first and last bytes in the 9-bit synchronization byte are not used for pattern matching, this error destroys only the first synchronization byte code. Taking this into consideration, the conventional approach provides that one bad sample combination is allowed in any of the three repeated 9-bit code sequences for achieving correct byte synchronization. However, two to four bad bit sample combinations in the 27-bit code pattern may cause synchronization failure or a mis-synchronization condition. More than four bad bit sample combinations in the 27-bit synchronization pattern causes a synchronization failure.
Thus, the conventional byte synchronization approach has the disadvantage of a long synchronization pattern (27 bits). Further, the probability of a synchronization failure and/or a mis-synchronization condition is not insignificant. For example, because one bad sample combination causes 2 code bit errors, the probability P.sub.sync fail of a synchronization failure and/or a mis-synchronization condition is calculated using the following equation: ##EQU2## where P.sub.err is obtained from Equation (2), and n=27 and m=1. Using the P.sub.err value from FIG. 6, P.sub.sync fail is calculated as shown in FIG. 16 (curve 161). From FIG. 6, P.sub.sync fail is 3.1.times.10.sup.-6 for an SNR=16 dB. Further still, write magnet trimming techniques are required for writing the special synchronization pattern.
Consequently, what is needed is a system and a method that uses a shorter synchronization pattern while providing a greater byte synchronization certainty than conventional byte synchronization approaches without requiring write magnet trimming for writing the synchronization pattern.